description designed for pulse width modulated (pwm) control of two dc motors, the a4954 is capable of peak output currents to 2 a and operating voltages to 40 v. input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied pwm control signals. internal synchronous rectification control circuitry is provided to lower power dissipation during pwm operation. internal circuit protection includes overcurrent protection, motor lead short to ground or supply, thermal shutdown with hysteresis, undervoltage monitoring of v bb , and crossover- current protection. the a4954 is provided in a low-profile 16-pin tssop package with exposed thermal pad (suffix lp) that is lead (pb) free, with 100% matte tin leadframe plating. a4954-ds, rev. 4 features and benefits ? low r ds(on) outputs ? overcurrent protection (ocp) ? motor short protection ? motor lead short to ground protection ? motor lead short to battery protection ? low power standby mode ? adjustable pwm current limit ? synchronous rectification ? internal undervoltage lockout (uvlo) ? crossover-current protection dual full-bridge dmos pwm motor driver package: 16-pin tssop with exposed thermal pad (suffix lp) functional block diagram not to scale a4954 control logic lss34 out3 vbb in3 in4 charge pump osc disable uvlo vref34 7v gnd tsd 10 control logic lss12 out1 out2 vbb in1 in2 charge pump osc disable load supply uvlo vref12 7v gnd (optional) (optional) tsd 10 out4
dual full-bridge dmos pwm motor driver a4954 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal list table number name function 1 gnd ground 2 vref34 analog input for bridge 3-4 3 in3 logic input 3 4 in4 logic input 4 5 in2 logic input 2 6 in1 logic input 1 7 vref12 analog input for bridge 1-2 8 gnd ground 9 vbb load supply voltage 10 out1 dmos full bridge output 1 11 lss12 power return ? sense resistor connection for bridge 1-2 12 out2 dmos full bridge output 2 13 out3 dmos full bridge output 3 14 lss34 power return ? sense resistor connection for bridge 3-4 15 out4 dmos full bridge output 4 16 vbb load supply voltage ? pad exposed pad for enhanced thermal dissipation pin-out diagram absolute maximum ratings characteristic symbol notes rating unit load supply voltage v bb 40 v logic input voltage range v in ?0.3 to 6 v v ref input voltage range v ref ?0.3 to 6 v sense voltage (lssx pin) v s ?0.5 to 0.5 v motor outputs voltage v out ?2 to 42 v output current i out duty cycle = 100% 2 a transient output current i out t w < 500 ns 5 a operating temperature range t a temperature range e ?40 to 85 c maximum junction temperature t j (max) 150 c storage temperature range t stg ?55 to 150 c selection guide part number packing a4954elptr-t 4000 pieces per 13-in. reel a4954elp-t 96 pieces per tube thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja on 2-layer pcb with 3.8 in 2 . exposed 2-oz. copper each side 43 oc/w on 4-layer pcb based on jedec standard 34 oc/w *additional thermal information available on the allegro website. gnd vref34 in3 in4 in2 in1 vref12 gnd vbb out4 lss34 out3 out2 lss12 out1 vbb 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pad
dual full-bridge dmos pwm motor driver a4954 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics valid at t j = 25c, unless otherwise specified characteristics symbol test conditions min. typ. max. unit general load supply voltage range v bb 8 ? 40 v r ds(on) sink + source total r ds(on) i out = |1.5 a|, t j = 25c ? 0.8 1.12 i out = |1.5 a|, t j = 125c ? 1.28 1.8 load supply current i bb f pwm < 30 khz ? 10 ? ma low power standby mode ? ? 10 a body diode forward voltage v f source diode, i f = ?1.5 a ? ? 1.5 v sink diode, i f = 1.5 a ? ? 1.5 v logic inputs logic input voltage range v in(1) 2.0 ? ? v v in(0) ? ? 0.8 v v in(standby) low power standby mode ? ? 0.4 v logic input current i in(1) v in = 2.0 v ? 40 100 a i in(0 )v in = 0.8 v ? 16 40 a logic input pull-down resistance rr r logic(pd) v in = 0 v = in1 = in2 = in3 = in4 ? 50 ? k input hysteresis v hys ? 250 550 mv timing crossover delay t cod 50 ? 500 ns v ref input voltage range v ref 0?5v current gain a v v ref / i ss , v ref = 5 v 9.5 ? 10.5 v/v v ref / i ss , v ref = 2.5 v 9.0 ? 10.0 v/v v ref / i ss , v ref = 1 v 8.0 ? 10.0 v/v blank time t blank 234 s constant off-time t off 16 25 34 s standby timer t st in1 = in2 = in3 = in4 < v in(standby) ? 1 1.5 ms power-up delay t pu ??30 s protection circuits uvlo enable threshold v bbuvlo v bb increasing 7 7.5 7.95 v uvlo hysteresis v bbuvlohys ? 500 ? mv thermal shutdown temperature t jtsd temperature increasing ? 160 ? c thermal shutdown hysteresis t tsdhys recovery = t jtsd ? t tsdhys ?15?c
dual full-bridge dmos pwm motor driver a4954 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance pwm control timing diagram pwm control truth table in1, in3 in2, in4 10 v s > v ref out1, out3 out2, out4 function 0 1 false l h reverse 1 0 false h l forward 0 1 true h/l l chop (mixed decay), reverse 1 0 true l h/l chop (mixed decay), forward 1 1 false l l brake (slow decay) 0 0 false z z coast, enters low power standby mode after 1 ms note: z indicates high impedance. reverse/ fast decay reverse/ slow decay forward/ fast decay forward/ slow decay gnd gnd +i reg 0 a -i reg in1, in3 in2, in4 i outx v in(1) v in(1)
dual full-bridge dmos pwm motor driver a4954 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description device operation the a4954 is designed to operate two dc motors. the output drivers are all low-r ds(on) , n-channel dmos drivers that feature internal synchronous rectification to reduce power dissipation. the current in each of the two output full bridges is regulated with fixed off-time pulse width modulated (pwm) control cir- cuitry. the in1-in2 and in3-in4 inputs allow two-wire control for each bridge. protection circuitry includes internal thermal shutdown, and pro- tection against shorted loads, or against output shorts to ground or supply. undervoltage lockout prevents damage by keeping the outputs off until the driver has enough voltage to operate nor- mally. standby mode low power standby mode is activated when all four input (inx) pins are low for longer than 1 ms. low power standby mode disables most of the internal circuitry, including the charge pump and the regulator. when the a4954 is coming out of standby mode, the charge pump should be allowed to reach its regulated voltage (a maximum delay of 200 s) before any pwm com- mands are issued to the device. internal pwm current control initially, a diagonal pair of source and sink fet outputs are enabled and current flows through the motor winding and the optional external current sense resistor, r sx . when the voltage across r sx equals the comparator trip value, then the current sense comparator resets the pwm latch. the latch then turns off the sink and source fets (mixed decay mode). v ref the maximum value of current limiting is set by the selection of r sx and the voltage at the vrefx pin in each channel. the transconductance function is approximated by the maximum value of current limiting, i tripmax (a), which is set by: i tripmax = a v r s v ref where v ref is the input voltage on the vrefx pin (v) and r s is the resistance of the sense resistor ( ) on the corresponding lssx terminal. overcurrent protection a current monitor will protect the ic from damage due to output shorts. if a short is detected, the ic will latch the fault and dis- able the outputs. each channel has independent ocp protection. the fault latch can only be cleared by coming out of low power standby mode or by cycling the power to vbb. during ocp events, absolute maximum ratings may be exceeded for a short period of time before the device latches. shutdown if the die temperature increases to approximately 160c, the full bridge outputs will be disabled until the internal temperature falls below a hysteresis, t tsdhys , of 15c. internal uvlo is present on vbb to prevent the output drivers from turning-on below the uvlo threshold. braking the braking function is implemented by driving the device in slow decay mode, which is done by applying a logic high to both inputs of both channels, after a bridge-enable chop command (see pwm control truth table). because it is possible to drive current in both directions through the dmos switches, this con- figuration effectively shorts-out the motor-generated bemf, as long as the chop command is asserted. the maximum current can be approximated by v bemf / r l . care should be taken to ensure that the maximum ratings of the device are not exceeded in worse case braking situations: high speed and high-inertia loads.
dual full-bridge dmos pwm motor driver a4954 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com synchronous rectification when a pwm off-cycle is triggered by an internal fixed off-time cycle, load current will recirculate. the a4954 synchronous rec- tification feature turns-on the appropriate dmosfets during the current decay, and effectively shorts out the body diodes with the low r ds(on) driver. this significantly lowers power dissipation. when a zero current level is detected, synchronous rectification is turned off to prevent reversal of the load current. mixed decay operation the bridges operate in mixed decay mode. referring to the lower panel of the figure below, as the trip point is reached, the device goes into fast decay mode for 50% of the fixed off-time period. after this fast decay portion the device switches to slow decay mode for the remainder of the off-time. during transitions from fast decay to slow decay, the drivers are forced off for the crossover delay, t cod . this feature is added to prevent shoot- through in the bridge. during this ?dead time? portion, synchro- nous rectification is not active, and the device operates in fast decay and slow decay only. mixed decay mode operation v phase i out i out + ? 0 see enlargement a enlargement a t cod t cod t cod fixed off-time, t off = 25 s fast decay slow decay i trip 0.50 t off 0.50 t off
dual full-bridge dmos pwm motor driver a4954 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information sense pins (lssx) in order to use pwm current control, a low-value resistor is placed between the lssx pin and ground for current sensing pur- poses. to minimize ground-trace ir drops in sensing the output current level, the current sensing resistor should have an indepen- dent ground return to the star ground point. this trace should be as short as possible. for low-value sense resistors, the ir drops in the pcb can be significant, and should be taken into account. when selecting a value for the sense resistor be sure not to exceed the maximum voltage on the lssx pin of 500 mv at maximum load. during overcurrent events, this rating may be exceeded for short durations. ground a star ground should be located as close to the a4954 as possible. the copper ground plane directly under the exposed thermal pad of the device makes a good location for the star ground point. the exposed pad can be connected to ground for this purpose. layout the pcb should have a thick ground plane. for optimum electrical and thermal performance, the a4954 must be soldered directly onto the board. on the underside of the a4954 package is an exposed pad, which provides a path for enhanced thermal dis- sipation. the thermal pad must be soldered directly to an exposed surface on the pcb in order to achieve optimal thermal conduc- tion. thermal vias are used to transfer heat to other layers of the pcb. the load supply pin, vbb, should be decoupled with an electro- lytic capacitor (typically 100 f) in parallel with a lower valued ceramic capacitor placed as close as practicable to the device. out3 out2 rs12 gnd gnd gnd c1 bulk c2 capacitance vbb out4 out1 rs34 gnd v bb 1 pad a4954 r s12 c1 c2 vbb out4 lss34 out3 out2 lss12 out1 vbb vref34 in3 in4 in2 in1 vref12 gnd gnd r s34 bill of materials item reference value units description 1 rs12, rs34 0.25 (for v ref = 5 v, i out = 2 a) 2512, 1 w, 1% or better, carbon film chip resistor 2 c1 0.22 f x5r minimum, 50 v or greater 3 c2 100 f electrolytic, 50 v or greater
dual full-bridge dmos pwm motor driver a4954 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 16-pin tssop with exposed thermal pad a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 16x 0.65 bsc 0.25 bsc 2 1 16 5.000.10 4.400.10 6.400.20 gauge plane seating plane a terminal #1 mark area b for reference only; not for tooling use (reference mo-153 abt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b c exposed thermal pad (bottom surface); dimensions may vary with device 6.10 0.65 0.45 1.70 3.00 3.00 16 2 1 reference land pattern layout (reference ipc7351 sop65p640x110-17m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view c branded face 3 nom 3 nom
dual full-bridge dmos pwm motor driver a4954 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2010-2013, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 4 august 6, 2012 update pwm table
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